CAD method for arranging via-holes, a CAD tool, photomasks...

Details CAD method for arranging via-holes, a CAD tool, photomasks... CAD method for arranging via-holes, a CAD tool, photomasks...

2006-12-05

2006-12-05

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C438S618000, C257S773000

Reexamination Certificate

active

07146597

ABSTRACT:
A design method encompasses: determining a direction of a subject wiring level in a multi-level interconnection of semiconductor integrated circuit as a subject-level priority direction; designing a layout of the subject wiring level, by placing a subject-level strip extending along the subject-level priority; generating a subject-level extension extending in a different direction of the subject-level priority direction, from a termination of the subject-level strip; allocating via-holes in the subject-level extension; and designing a layout of a neighboring wiring level of the subject wiring level, by placing a neighboring-level strip extending along the same direction as the subject-level extension extends, so that a termination of the neighboring-level strip can include the via-holes.

REFERENCES:
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patent: 2005/0240894 (2005-10-01), Teig et al.
patent: 2001-284455 (2001-10-01), None

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