Caching of microcode emulation memory

Details Caching of microcode emulation memory Caching of microcode emulation memory

2007-05-29

2010-06-08

Kim, Matt (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S152000, C711S163000, C712S208000

Reexamination Certificate

active

07734873

ABSTRACT:
A processor includes a cache hierarchy including a level-1 cache and a higher-level cache. The processor maps a portion of physical memory space to a portion of the higher-level cache, executes instructions, at least some of which comprise microcode, allows microcode to access the portion of the higher-level cache, and prevents instructions that do not comprise microcode from accessing the portion of the higher-level cache. The first portion of the physical memory space can be permanently allocated for use by microcode. The processor can move one or more cache lines of the first portion of the higher-level cache from the higher-level cache to a first portion of the level-1 cache, allow microcode to access the first portion of the first level-1 cache, and prevent instructions that do not comprise microcode from accessing the first portion of the first level-1 cache.

REFERENCES:
patent: 4901235 (1990-02-01), Vora et al.
patent: 5132927 (1992-07-01), Lenoski et al.
patent: 5278973 (1994-01-01), O'brien et al.
patent: 5649112 (1997-07-01), Yeager et al.
patent: 5671356 (1997-09-01), Wang
patent: 5796972 (1998-08-01), Johnson et al.
patent: 5826052 (1998-10-01), Stiles et al.
patent: 5864689 (1999-01-01), Tran
patent: 5889978 (1999-03-01), Jayakumar
patent: 5950012 (1999-09-01), Shiell et al.
patent: 6125412 (2000-09-01), Picard et al.
patent: 6141740 (2000-10-01), Mahalingaiah et al.
patent: 6397301 (2002-05-01), Quach et al.
patent: 6643800 (2003-11-01), Safford et al.
patent: 6745306 (2004-06-01), Willman et al.
patent: 6754765 (2004-06-01), Chang et al.
patent: 7095342 (2006-08-01), Hum et al.
patent: 7370243 (2008-05-01), Grohoski et al.
patent: 2001/0052066 (2001-12-01), Lee et al.
patent: 2002/0069328 (2002-06-01), Chauvel
patent: 2005/0055510 (2005-03-01), Hass et al.
patent: 2005/0188156 (2005-08-01), Mukker et al.
patent: 2006/0174079 (2006-08-01), Kajihara
patent: 2008/0256336 (2008-10-01), Henry et al.
patent: 2008/0263339 (2008-10-01), Kriegel et al.
patent: 97/13194 (1997-01-01), None
International Search Report and Written Opinion mailed Oct. 1, 2008 for International Application No. PCT/US2008/006746 filed May 28, 2008.
Jacob, et al. “A look at several memory management units, TLB-refill mechanisms, and page table organizations” ACM Proceedings of ASPLOS-VIII, San Jose, CA USA, Oct. 3-7, 1998, pp. 295-306.

Affiliated with

Also associated with

Rating

Caching of microcode emulation memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Caching of microcode emulation memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Caching of microcode emulation memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4231672