Caching in multicore and multiprocessor architectures

Details Caching in multicore and multiprocessor architectures Caching in multicore and multiprocessor architectures

2007-05-25

2010-08-10

Peugh, Brian R (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07774553

ABSTRACT:
A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some of the memory interfaces providing access paths to the main memory for multiple of the cache memories. Each of the memory interfaces is associated with a corresponding portion of the main memory, and includes a directory controller for the portion of the main memory.

REFERENCES:
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5119485 (1992-06-01), Ledbetter et al.
patent: 5148536 (1992-09-01), Witek et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5241639 (1993-08-01), Feldbrugge
patent: 5430888 (1995-07-01), Witek et al.
patent: 5596754 (1997-01-01), Lomet
patent: 5893153 (1999-04-01), Tzeng et al.
patent: 5960461 (1999-09-01), Frank et al.
patent: 6332178 (2001-12-01), Dean et al.
patent: 6651145 (2003-11-01), Jamil et al.
patent: 7200713 (2007-04-01), Cabot et al.
patent: 7394288 (2008-07-01), Agarwal
patent: 7461236 (2008-12-01), Wentzlaff
patent: 7539845 (2009-05-01), Wentzlaff et al.
patent: 2002/0129208 (2002-09-01), Barroso et al.
patent: 2004/0008677 (2004-01-01), Cen
patent: 2005/0071573 (2005-03-01), Dodson et al.
patent: 2005/0144390 (2005-06-01), Mattina et al.
patent: 2006/0179429 (2006-08-01), Eggers et al.
patent: 2007/0055825 (2007-03-01), Blumrich et al.
patent: WO 2004/072796 (2004-08-01), None
Agarwal, Anant. “Raw Computation,”Scientific Americanvol. 281, No. 2: 44-47, Aug. 1999.
Taylor, Michael Bedford et. al., “Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,”Proceedings of International Symposium on Computer Architecture, Jun. 2004.
Taylor, Michael Bedford et. al., “Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures,”Proceedings of the International Symposium on High Performance Computer Architecture, Feb. 2003.
Taylor, Michael Bedford et. al., “A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network,”Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 2003.
Taylor, Michael Bedford et. al., “The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,”IEEE Micro, pp. 25-35, Mar.-Apr. 2002.
Lee, Walter et. al., “Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,”Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS-VIII), San Jose, CA, Oct. 4-7, 1998.
Kim, Jason Sungtae et. al., “Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,”International Symposium on Low Power Electronics and Design, Seoul, Korea, Aug. 25-27, 2003.
Barua, Rajeev et. al., “Compiler Support for Scalable and Efficient Memory Systems,”IEEE Transactions on Computers, Nov. 2001.
Waingold, Elliot et. al., “Baring it all to Software: Raw Machines,”IEEE Computer, pp. 86-93, Sep. 1997.
Lee, Walter et. al., “Convergent Scheduling,”Proceedings of the 35thInternational Symposium on Microarchitecture, Istanbul, Turkey, Nov. 2002.
Wentzlaff, David and Anant Agarwal, “A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation,”MIT/LCS Technical Report LCS-TR-944, Apr. 2004.
Suh, Jinwoo et. al., “A Performance Analysis of PIM, Stream Processing , and Tiled Processing on Memory-Intensive Signal Processing Kernels,”Proceedings of the International Symposium on Computer Architecture, Jun. 2003.
Barua, Rajeev et. al., “Maps: A Compiler-Managed Memory System for Raw Machines,”Proceedings of the Twenty-Sixth International Symposium on Computer Architecture(ISCA-26), Atlanta, GA, Jun. 1999.
Barua, Rajeev et. al., “Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,”Proceedings of the Fifth International Conference on High Performance Computing, Chennai, India, Dec. 17-20, 1998.
Agarwal, A. et. al., “The Raw Compiler Project,”Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, Aug. 21-23, 1997.
Taylor, Michael Bedford et. al., “Scalar Operand Networks,”IEEE Transactions on Parallel and Distributed Systems(Special Issue on On-Chip Networks), Feb. 2005.
Taylor, Michael. The Raw Prototype Design Document V5.01 [online]. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Sep. 6, 2004 [retrieved on Sep. 25, 2006]. Retrieved from the Internet: <ftp://ftp.cag.lcs.mit.edu/pub/raw/documents/RawSpec99.pdf>.
Moritz, Csaba Andras et. al., “Hot Pages: Software Caching for Raw Microprocessors,”MIT/LCS Technical Memo LCS-TM-599, Aug. 1999.
Wenbin Yao, Dongsheng Wang, Weimin Zheng, and Songliu Guo, “Architecture Design of a Single-chip Multiprocessor”, Proceedings of the International Conference on High Performance Computing and Applications, Aug. 8-10, 2004, Shanghai, P.R. China.
Anant Agarwal, Richard Simoni, John Hennessy, and Mark Horowitz. “An Evaluation of Directory Schemes for Cache Coherence.” In Proceedings of the 15th Annual Symposium on Computer Architecture, Jun. 1988, ACM, SIGARCH.
David Chaiken, John Kubiatowicz, and Anant Agarwal. “LimitLESS Directories: A Scalable Cache Coherence Scheme.” Proceedings of ASPLOS-1V, Apr. 1991.
David Lars Chaiken, MS thesis, MIT 1990.
Chang, J. and Sohi, G. S. Cooperative Caching for Chip Multiprocessors. In Proceedings of the 33rd Annual international Symposium on Computer Architecture (Jun. 17-21, 2006). International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Washington, DC, 264-276.
S. Kaneko et al. A 600mhz single-chip multiprocessor with 4.8gb/s internal shared pipelined bus and 512kb internal memory. IEEE Journal of Solid-State Circuits, 39(1):184—193, 2004.
Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In Proceedings of the 27th ACM International Symposium on Computer Architecture. Vancouver, CA, Jun. 2000.
Speight, E., Shafi, H., Zhang, L., and Rajamony, R. 2005. Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors. SIGARCH Comput. Archit. News 33, 2 (May 2005), 346-356.
Takahashi, M., Takano, H., Kaneko, E., and Suzuki, S. 1996. A Shared-bus Control Mechanism and a Cache Coherence Protocol for a High-performance On-chip Multiprocessor. In Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture (Feb. 3-7, 1996).
Donald Yeung, John Kubiatowicz, and Anant Agarwal. MGS: A Multigrain Shared Memory System. Proceedings of the 23rd Annual International Symposium on Computer Architecture, pp. 45-56, May 1996.
David Chaiken, Craig Fields, Kiyoshi Kurihara, and Anant Agarwal. “Directory-Based Cache-Coherence in Large-Scale Multiprocessors.” IEEE Computer, Jun. 1990.
John Kubiatowicz, David Chaiken, and Anant Agarwal. Closing the Window of Vulnerability in Multiphase Memory Transactions. In ASPLOS 1992.
David Chaiken and Anant Agarwal, “Software-Extended Coherent Shared Memory: Performance and Cost,” in Proceedings 21st Annual International Symposium on Computer Architecture (ISCA'94), Apr. 1994.
John Kubiatowicz, David Chaiken, Anant Agarwal, Arthur Altman, Jonathan Babb, David Kranz, Beng-Hong Lim, Ken Mackenzie, John Piscitello, and Donald Yeung. “The Alewife CMMU: Addressing the Multiprocessor Communications Gap,” in Hotchips, Aug. 1994.
Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Ken Mackenzie, and Donald Yeung, “The

Affiliated with

Also associated with

Rating

Caching in multicore and multiprocessor architectures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Caching in multicore and multiprocessor architectures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Caching in multicore and multiprocessor architectures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4150602