Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1998-05-18
1999-12-07
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
36523008, 36523003, G06F 1200, G11C 800
Patent
active
060000074
ABSTRACT:
A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.
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Leung Wingyu
Tam Kit Sang
Cabeca John W.
Chow Christopher S.
Monolithic System Technology, Inc.
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