Caching device for NAND flash translation layer

Details Caching device for NAND flash translation layer Caching device for NAND flash translation layer

2011-08-30

2011-08-30

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

Reexamination Certificate

active

08010770

ABSTRACT:
A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

REFERENCES:
patent: 6115547 (2000-09-01), Ghatate et al.
patent: 2004/0186946 (2004-09-01), Lee
patent: 2005/0149896 (2005-07-01), Madurawe
patent: 1249670 (2006-02-01), None
patent: 1253564 (2006-04-01), None

Affiliated with

Also associated with

Rating

Caching device for NAND flash translation layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Caching device for NAND flash translation layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Caching device for NAND flash translation layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2677356