Cached-counter arrangement in which off-chip counters are...

Details Cached-counter arrangement in which off-chip counters are... Cached-counter arrangement in which off-chip counters are...

2006-06-06

2006-06-06

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S502000, C377S044000

Reexamination Certificate

active

07058839

ABSTRACT:
In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter in main memory is updated using the cache memory counter value. This arrangement economizes on the use of main memory access bandwidth.

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