Cacheable interface control registers for high speed data transf

Details Cacheable interface control registers for high speed data transf Cacheable interface control registers for high speed data transf

1997-06-09

1999-09-14

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 56, 710 54, 711138, 711171, G06F 1314

Patent

active

059516577

ABSTRACT:
A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.

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David A. Patterson, John L. Hennessey, Computer Architecture A Quantitative Approach, Morgan Kauffman Publishers, Inc., San Mateo, California, p. 471, 1990.

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