Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-12-19
2000-09-19
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711122, 711119, 711120, 711128, G06F 1200
Patent
active
061227099
ABSTRACT:
A cache memory system including a cache memory having a plurality of cache lines. An index portion of a tag array includes an n-bit pointer entry for every cache line. A shared tag portion of a tag array includes a number of entries, where each entry includes shared tag information that is shared among a plurality of the cache lines. Each n-bit pointer in the index portion of the tag array points into an entry in the shared tag portion.
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Hetherington Ricky C.
Kasinathan Meera
Wicki Thomas M.
Bataille Pierre-Michel
Cabeca John W.
McKay Philip
Sun Microsystems Inc.
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