Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2005-07-05
2005-07-05
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S216000, C711S133000
Reexamination Certificate
active
06915373
ABSTRACT:
In a cache system a steering array indirect maps queries to the cache cells, and a cyclic replacement mechanism allocates the cache cells for replacement in the cache. The cache system has a hash mechanism, a steering array and a cyclic replacement counter. The hash mechanism computes a hash value from arguments in the query. The cache has a plurality of cache cells, and each cell has an answer and a usage bit indicating whether the cell is in use. The steering array stores a cache index based on the hash value, and the cache index points to a cache cell that may contain the answer to the query. The cyclic replacement counter addresses each cell in the cache to determine if the cell is still in use or may store a new answer.
REFERENCES:
patent: 5353425 (1994-10-01), Malamy et al.
patent: 5930819 (1999-07-01), Hetherington et al.
patent: 6161166 (2000-12-01), Doing et al.
Bragdon Reginald G.
Merchant & Gould P.C.
Microsoft Corporation
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