Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Reexamination Certificate
2011-07-05
2011-07-05
Portka, Gary J (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
C711S127000, C711S140000, C711S207000
Reexamination Certificate
active
07975093
ABSTRACT:
A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.
REFERENCES:
patent: 5680572 (1997-10-01), Akkary et al.
patent: 5907860 (1999-05-01), Garibay, Jr. et al.
patent: 6138206 (2000-10-01), Fisher et al.
patent: 7257673 (2007-08-01), Emerson et al.
Basto Carlos
Van De Waerdt Jan-Willem
NXP B.V.
Portka Gary J
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