Cache with an extended single cycle read/write system and method

Details Cache with an extended single cycle read/write system and method Cache with an extended single cycle read/write system and method

1996-06-06

1997-03-11

Swann, Tod R.

Excavating

395872, 395455, 395500, 371 511, 364DIG1, G06F 1316

Patent

active

056110723

ABSTRACT:
A method for updating a LRU array in a cache having a RAM. The LRU array has a self-timing signal for the read operation of the LRU array, in conjunction with a cache RAM read cycle. According to the method, first, a cache RAM cycle is begun. Then, it is determined whether a hit condition exists with respect to a tag associated with the LRU array. A self-timing signal is generated if the hit condition exists. In response to the self-timing signal, and in the cache RAM read cycle, an LRU write operation is begun with respect to the LRU array. The LRU write operation includes the steps of providing a write signal to the LRU array, and of precharging the LRU array. The LRU write operation is extended for a time sufficient for the precharging of the LRU bit line to complete. This can result in the LRU write operation extending into the next cache cycle. Additionally, the LRU array may be provided with an LRU dummy cell. Then, the LRU write operation is performed by additionally providing a write signal to the LRU dummy cell, so as to perform a dummy cell write operation, and the step of precharging the LRU array is performed based on the completion of the dummy cell write operation.

REFERENCES:
patent: 4967414 (1990-10-01), Lusch et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5218686 (1993-06-01), Thayer
patent: 5253358 (1993-10-01), Thoma, III et al.
patent: 5367659 (1994-11-01), Iyengar et al.
patent: 5371870 (1994-12-01), Goodwin et al.

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