Cache used both as cache and staging buffer

Details Cache used both as cache and staging buffer Cache used both as cache and staging buffer

2006-11-30

2009-11-24

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S113000, C711S118000

Reexamination Certificate

active

07624235

ABSTRACT:
In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

REFERENCES:
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patent: 6085263 (2000-07-01), Sharma et al.
patent: 6295582 (2001-09-01), Spencer
patent: 6772295 (2004-08-01), Spencer et al.
P.A. Semi, “The PWRficient Processor Family,” Oct. 2005, pp. 1-31.

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