Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1994-08-22
1998-05-05
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711114, G06F 1212
Patent
active
057490902
ABSTRACT:
A cache TAG RAM (20) has a TAG array (22, 24) for storing TAG addresses of data stored in a cache memory, and a valid bit array (26, 31). In the cache TAG RAM (20), a valid bit is set for each TAG address to indicate if the TAG address is valid. The valid bit array (26, 31) is located separate from the TAG array (22, 24). During power-up of the cache TAG RAM (20), a multiple step invalidation cycle is used to sequentially invalidate groups of columns of the valid bit array (26, 31). The multiple step invalidation cycle reduces the peak current during an invalidation cycle, thus reducing metal migration.
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Feng Taisheng
Raatz Donovan
Chan Eddie P.
Ellis Kevin L.
Hill Daniel D.
Motorola Inc.
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