Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-01-25
2004-08-10
Padmanabhan, Mano (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C713S324000
Reexamination Certificate
active
06775741
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cache system in a CPU, and more particularly to a cache system that can reduce the number of accesses to a tag memory used for detecting cache hits.
2. Description of the Related Art
CPUs generally contain a cache system. Main memory wherein are stored programs and data (hereinafter referred to as “data”) is provided external to the CPU, but access from the CPU to the external main memory is slow. Once the external main memory is accessed, the data stored therein are also stored in a cache memory within the CPU. When the same address is next accessed, the data stored in cache memory are used without the external main memory being accessed. The frequency of access from the CPU to the external main memory is thereby reduced and CPU performance can be improved.
In addition to data memory for storing data from the external memory, the cache system includes tag memory for storing an address whose data is stored in the data memory. When data access is generated by CPU, a cache hit determination is performed within the CPU, wherein the address data in the tag memory are read and it is determined whether that address data match the address to be accessed. If the address data read from tag memory match the address to be accessed and a valid data-indicating flag in the tag memory is valid, this is determined to be a cache hit. Then, Data within the internal data memory are read and the external main memory is not accessed. On the other hand, if the address data read from tag memory do not match the address to be accessed or the valid data-indicating flag in the tag memory is invalid, this is determined to be a cache miss. Then, the external main memory is accessed, those data are stored in the internal data memory, and the address information and valid data-indicating flag are stored in the tag memory. The address information within the tag memory is also called the address tag and an upper address is stored in the tag memory identified by a lower address. In addition to this address tag, a valid data bit indicating whether that address tag is valid is stored within the tag memory.
As discussed above, the tag memory within the CPU is accessed upon each memory access and a cache determination is performed. Meanwhile, in order for speed, a high-speed memory such as SRAM is used for the tag memory and data memory provided in the cache system. Consequently, considerable power is consumed by each tag memory access. This type of power consumption becomes a problem that cannot be ignored when the CPU is installed in a portable telephone or portable information terminal.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a cache system that can reduce the number of accesses to tag memory.
It is another object of the present invention to provide a cache system that can reduce the number of tag memory read operations.
It is another object of the present invention to provide a cache system that can reduce power consumption.
In order to achieve the abovementioned objects, a first aspect of the present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.
In the case where the tag memory address information commonly controls a plurality of data items with consecutive addresses, one item of address information within tag memory is used for the plurality of data items in common. Consequently, in the event of a request to access the address for the plurality of data items controlled by one item of address information in tag memory, tag memory is read and a cache hit determination is performed upon the first access of an address within that range of control. In the event of a subsequent request to access an address in the same range of control, however, tag memory is not read again because the address information within tag memory is the same as the preceding access. As a result, the number of redundant readings of tag memory can be reduced.
In the case of tag memory commonly controlling the abovementioned plurality of data items, there are a first and second constitution: in the first constitution the valid data bit comprises one bit and a plurality of data items are written collectively to the internal data memory from the external memory in the case of a cache miss; and in the second constitution the valid data bit comprises a plurality of bits (for example, the same number of bits as the plurality of data items), and in the case of a cache miss only the data items requested for access are written to the internal data memory from the external memory and corresponding valid data bits are updated.
In the case of the first constitution, tag memory is read and a hit determination is performed upon the first access to an address within the range of control of one item of address information within tag memory. Upon subsequent accesses to addresses within the same range of control, however, a cache hit is forcibly determined without reading tag memory and the corresponding data in the internal data memory are accessed because the plurality of corresponding data are already written to the internal data memory regardless of the abovementioned hit determination.
In the case of the second constitution, tag memory is read and a hit determination is performed upon the first access to an address within the range of control of one item of address information within tag memory; at the same time, the corresponding valid data bit is stored. Upon subsequent accesses to addresses within the same range of control, the hit determination is performed according to the valid data bit that was stored and without reading tag memory. At a cache hit, corresponding data within the internal data memory is accessed. At a cache miss, corresponding data in external memory is accessed, the accessed data is written to the internal data memory, and at the same time the valid data bit is updated to the valid state. Also, during the abovementioned cache miss, access to the internal memory is stopped.
In order to achieve the abovementioned objects, another aspect of the present invention is a cache system comprising: a data memory for holding a part of data stored in an external memory; a tag memory for holding address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid, in which the address information commonly controls a plurality of data items with consecutive addresses; and a cache controller that prohibits reading of the tag memory in a first case where an address to be accessed corresponds to data controlled by the same address information in tag memory as that for the preceding address to be accessed, and that allows reading of the tag memory and performs a cache hit determination in a second case where the address to be accessed corresponds to data controlled by different address information in tag memory from that for the preceding address to be accessed.
For the second and subsequent accesses of the plurality of data items controlled by the same address information in tag memory, the operation for reading tag memory is omitted and power consumption can therefore be decreased.
In a more preferable embodiment of the invention, the valid data bit comprises one bit in
Ebeshu Hidetaka
Tomatsuri Hideaki
Baker Paul
Padmanabhan Mano
Staas & Halsey , LLP
LandOfFree
Cache system with limited number of tag memory accesses does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache system with limited number of tag memory accesses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache system with limited number of tag memory accesses will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3350981