Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-04-18
2006-04-18
Banankhah, Majid (Department: 2195)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S136000, C711S141000, C711S145000, C711S160000, C711S125000
Reexamination Certificate
active
07032073
ABSTRACT:
Cache apparatus, including first and second cache memories, coupled to receive and hold context information from an external memory with respect to tasks, each task activated by one or more activating events, so that the context information is available for access by a processor in performing the tasks. The cache apparatus further includes a mapper, which is coupled to receive a classification of the tasks as fast and slow tasks. The mapper is adapted, upon receipt of one of the activating events for one of the fast tasks to be performed by the processor, to cause the context information with respect thereto to be received in the first cache memory, and upon receipt of one of the activating events for one of the slow tasks to be performed by the processor, to cause the context information with respect thereto to be received in the second cache memory.
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Mizrachi Shay
Oren Amit
Shalom Rafi
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