Cache system configurable for serial or parallel access dependin

Details Cache system configurable for serial or parallel access dependin Cache system configurable for serial or parallel access dependin

1998-06-11

2000-06-27

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1208

Patent

active

060818719

ABSTRACT:
A data processing system having a CPU (central processing unit), a system bus and a main memory connected to the system bus, comprises a cache memory connected to the system bus for storing a predetermined part of data stored at the main memory, a first path unit for coupling the CPU with the cache memory, a second path unit for connecting the CPU to the system bus, and controller for enabling one of the first and the second path units. In the data processing system, the main memory is accessed only if a cache miss occurs while the first path unit is enabled, and the main memory and the cache memory are accessed simultaneously while the second path unit is enabled.

REFERENCES:
patent: 5249282 (1993-09-01), Segers
patent: 5761715 (1998-06-01), Takahashi
patent: 5978888 (1999-11-01), Arimilli et al.

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