Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-11-22
1998-10-13
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711136, G06F 1212
Patent
active
058227598
ABSTRACT:
A cache memory system maintains an ordered linked list of cache items having scores that are positively correlated with frequencies of access and negatively correlated with a size that is determined as a number of bytes of each item plus an overhead associated with the linked list. In addition to data and linking pointers, the list segments each include a hit count and a byte count. In a method for managing cache memory forms the linked list by adding segments for newly requested data and deleting data having lowest scores. Upon a cache miss, a new list segment that is created for the requested data is positioned in the list by comparison with scores beginning at the head of the list. Upon a cache hit, the hit count is incremented and the segment is relocated, if necessary, using comparisons of scores of next higher segments.
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Chow Christopher S.
Swann Tod R.
Versant Object Technology
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