Cache subsystem with pseudo-packet switch

Details Cache subsystem with pseudo-packet switch Cache subsystem with pseudo-packet switch

1997-03-31

1999-10-26

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711143, 711144, G06F 1200

Patent

active

059745118

ABSTRACT:
A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus starts a memory read transaction, the host converts the virtual address of the memory read transaction to a physical address. The snoop logic circuit checks to see whether the physical address is in the bus cache and, if so, whether the data in the bus cache corresponding to address is valid. If there is a bus cache hit, the corresponding data is accessed from the bus cache and output onto the peripheral bus. However, if the snoop logic circuit does not find the physical address in the bus cache or finds that the data is invalid, the snoop logic circuit causes (1) the peripheral bus interface unit to perform a retry operation on the peripheral bus and (2) the cache controller to process a memory request to retrieve the requested data from the L1 cache, L2 cache (if any) or the main memory and store the requested data into the bus cache. In addition, when the device retries the memory read request, the bus cache will have the requested data so that the data can be immediately provided to the peripheral bus. Thus, in memory read transactions longer than a cache line, the data is provided on the peripheral bus in a pseudo-packet switched manner.

REFERENCES:
patent: 5072369 (1991-12-01), Theus et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5557769 (1996-09-01), Bailey et al.
patent: 5630094 (1997-05-01), Hayek et al.
patent: 5761725 (1998-06-01), Zeller et al.

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