Cache sub-array arbitration

Details Cache sub-array arbitration Cache sub-array arbitration

1996-04-29

1999-05-18

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711146, 711158, 711217, G06F12/08

Patent

active

059059990

ABSTRACT:
A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

REFERENCES:
patent: 4811306 (1989-03-01), Boning et al.
patent: 4914582 (1990-04-01), Bryg et al.
patent: 5249282 (1993-09-01), Segers
patent: 5353416 (1994-10-01), Olson
patent: 5359557 (1994-10-01), Aipperspach et al.
patent: 5361391 (1994-11-01), Westberg
patent: 5483645 (1996-01-01), Tran
patent: 5581734 (1996-12-01), DiBrino et al.
patent: 5604865 (1997-02-01), Lentz et al.
patent: 5640534 (1997-06-01), Liu et al.
patent: 5649144 (1997-07-01), Gostin et al.

Affiliated with

Also associated with

Rating

Cache sub-array arbitration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache sub-array arbitration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache sub-array arbitration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1769294