Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-09-23
1999-04-06
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
G06F 1208
Patent
active
058931465
ABSTRACT:
A cache including a tag storage which compares a portion of the tag address (a "mini-tag") to a respective portion of a request address is provided. If the mini-tag matches, then the way associated with the tag having a match is the way selected for conveying data bytes to the output of the cache. The mini-tag comparison is performed on a field of address bits different from the index field, and the comparison is performed in parallel with the index field decode. The way selection is qualified with the index field decode such that one set and one way of the set is selected for conveying bytes from the cache. The access time of the present cache structure is substantially similar to a direct-mapped cache. However, the present cache strucuture is a set-associative structure. The hit rate and thrashing insensitivity of a set-associative cache are maintained by the present cache.
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King , Jr. Conley B.
Kivlin B. Noel
Merkel Lawrence J.
Swann Tod R.
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