Cache residency test instruction

Details Cache residency test instruction Cache residency test instruction

2007-05-22

2007-05-22

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S154000

Reexamination Certificate

active

10609105

ABSTRACT:
A cache residency test instruction is described which, when executed by a processor unit, allows the processor unit to determine if a set of data resides in a cache memory that is communicatively coupled to the processor unit and communicate a result of the determination to software being executed on the processor unit.

REFERENCES:
patent: 5594864 (1997-01-01), Trauben
patent: 5696932 (1997-12-01), Smith
patent: 5828860 (1998-10-01), Miyaoku et al.
patent: 6052775 (2000-04-01), Panwar et al.
patent: 6382846 (2002-05-01), Lai et al.
patent: 6453278 (2002-09-01), Favor et al.
patent: 6560676 (2003-05-01), Nishimoto et al.
patent: 6681295 (2004-01-01), Root et al.

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