Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-03-28
2006-03-28
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S133000, C711S159000, C711S160000
Reexamination Certificate
active
07020748
ABSTRACT:
A method for identifying a least recently used cache entry in a cache. The method includes receiving a cache access request, determining whether the contents of the main memory address are present in the cache, associating, when the contents of the main memory address are not present in the cache, updating more significant bits of a pseudo least recently used pointer when the contents of the main memory address are not present in the cache, and updating more significant bits and less significant bits of the pseudo least recently used pointer when the contents of the main memory address are present in the cache. The cache access request is associated with a main memory address. The memory address has a set within the cache and the set includes a plurality of ways.
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“An Overview of the UltraSPARC© III Cu Processor—The UltraSPARC III Processor Moves to Copper Technology” Version 1.1, Sun Microsystems, Inc. Jun. 2002.
Hamilton & Terrile LLP
Portka Gary
Song Jasmine
Sun Microsystems Inc.
Terrile Stephen A.
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