Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-17
1998-04-07
Ray, Gopal C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711117, 711118, 711128, 711134, 711135, 711136, 711144, 711154, 711158, 711159, 711160, G06F 1212
Patent
active
057377529
ABSTRACT:
An n-way set-associative cache (where n is an integer greater than 1), includes a replacement mechanism for selecting a cache line for replacement. Each cache line has an associated priority tag indicating a user-defined priority for that cache line The replacement mechanism comprises an apparatus for selecting a cache line with the lowest user-defined priority in a current set of cache lines, and apparatus (e.g. based on recency of usage) for choosing between cache lines of equal priority if there is more than one cache line with said lowest user-defined priority in the current set.
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Darbe Valerie
International Computers Limited
Ray Gopal C.
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