Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-10
1998-09-22
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711142, 711143, 711145, 711154, G06F 1200
Patent
active
058130284
ABSTRACT:
A method for invalidating a line in a cache block in a cache memory during a cache write operation, wherein the cache block includes two or more lines of data sharing a common tag address. The method involves generating a read miss request with respect to one or more lines in the cache block, including a tag and block address and an invalidation control bit. When the invalidation control bit is on, the invalidation control bit causes the setting of the validity bits, for those lines in the cache block other than the one or more lines for which the read miss request is generated, to invalid. When the invalidation control bit is off, the invalidation control bit prevents the resetting of the validity bits, for those lines in the cache block other than the one or more lines for which the read miss request is generated. The method involves generating a read miss request with respect to one or more lines in the cache block, including a tag and block address and an invalidation control bit, the invalidation control bit causing the setting to invalid of the validity bits for those lines in the cache block other than the one or more lines for which the read miss request is generated when the invalidation control bit is on, and the invalidation control bit preventing the resetting of the validity bits for those lines in the cache block other than the one or more lines for which the read miss request is generated when the invalidation control bit is off. For the read miss request, the tag and block address of the read miss request are compared against the tag and block address of other, pending read miss requests. If a match is found in the comparison, the line invalidation control bit is set to off for the read miss request, but if a match is not found, the line invalidation control bit is set to on for the read miss request.
REFERENCES:
patent: 3623017 (1971-11-01), Lowell
patent: 3715729 (1973-02-01), Mercy
patent: 4254475 (1981-03-01), Cooney et al.
patent: 4803621 (1989-02-01), Kelly
patent: 4814981 (1989-03-01), Rubinfeld
patent: 4816700 (1989-03-01), Imel
patent: 4819164 (1989-04-01), Branson
patent: 4821229 (1989-04-01), Jauragui
patent: 4910656 (1990-03-01), Scales et al.
patent: 4912632 (1990-03-01), Gach et al.
patent: 4967414 (1990-10-01), Lusch et al.
patent: 4985640 (1991-01-01), Grochowski et al.
patent: 5079440 (1992-01-01), Roberts et al.
patent: 5133058 (1992-07-01), Jensen
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5218686 (1993-06-01), Theya
patent: 5233702 (1993-08-01), Emma et al.
patent: 5251311 (1993-10-01), Kasai
patent: 5253358 (1993-10-01), Thoma, III et al.
patent: 5301298 (1994-04-01), Kagan et al.
patent: 5325511 (1994-06-01), Collins et al.
patent: 5367659 (1994-11-01), Iyenga et al.
patent: 5367660 (1994-11-01), Gat et al.
patent: 5371870 (1994-12-01), Goodwin
patent: 5379379 (1995-01-01), Becker et al.
patent: 5386547 (1995-01-01), Jouppi
patent: 5423019 (1995-06-01), Lin
patent: 5530933 (1996-06-01), Frink
patent: 5537570 (1996-07-01), Tran
patent: 5555392 (1996-09-01), Chaput et al.
patent: 5611072 (1997-03-01), Tran
IBM Technical Disclosure Bulletin Double Frequency Clock Generator) Aug. 1991 Nishihara.
"Advanced Clock Controller Cuts Power Needs, Size of Static CMOS Systems" (Electronic Design Oct. 04, 1984) Curtis A Mroz & Walt Niewierski Oct. 1984.
"Clocking Subsystems Pace High Performance Logic" (Computer Design Nov. 1, 1987) Jacob Shuhani & Don Draper Nov. 1987.
Microprocessor and Peripheral Handbook vol. 1 Microprocessor Intel 1987.
Minoru et al, "Invalidation Processing System for Cache" Memory.sup.3, Jan. 31, 1900 (JP 9021095) Japanese Abstract.
Agarwala Sanjive
Tran Hiep
Donaldson Richard L.
Kesterson James C.
Moore J. Dennis
Swann Tod R.
Texas Instruments Incorporated
LandOfFree
Cache read miss request invalidation prevention method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache read miss request invalidation prevention method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache read miss request invalidation prevention method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1635409