Cache predictor for simultaneous multi-threaded processor...

Details Cache predictor for simultaneous multi-threaded processor... Cache predictor for simultaneous multi-threaded processor...

2006-05-02

2006-05-02

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S125000, C711S204000

Reexamination Certificate

active

07039768

ABSTRACT:
A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of thread valid bits that are individually assigned to one of the multiple threads. Particular ones of the thread valid bits are set in each EA Dir to indicate when an instruction block the thread is cached within the particular way with which the EA Dir is associated. When a cache line request for a particular thread is received, a cache hit is predicted when the EA of the request matches the EA in the EA Dir and the cache line is selected from the way associated with the EA Dir who has the thread valid bit for that thread set. Early way selection is thus achieved since the way selection only requires a check of the thread valid bits.

REFERENCES:
patent: 5918044 (1999-06-01), Levitan et al.
patent: 6161166 (2000-12-01), Doing et al.
patent: 6263404 (2001-07-01), Borkenhagen et al.

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