Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-03-31
2001-08-14
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000
Reexamination Certificate
active
06275904
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the field of computer systems, and in particular, to an apparatus and method for providing instructions which facilitate the control of cache accesses while minimizing cache pollution.
2. Description of the Related Art
The use of a cache memory with a processor facilitates the reduction of memory access time. The fundamental idea of cache organization is that by keeping the most frequently accessed instructions and data in the fast cache memory, the average memory access time will approach the access time of the cache. To achieve the optimal tradeoffs between cache size and performance, typical processors implement a cache hierarchy, that is, different levels of cache memory. The different levels of cache correspond to different distances from the processor core. The closer the cache is to the processor, the faster the data access. However, the closer the cache is to the processor, the more costly it is to implement. As a result, the closer the cache level, the faster and smaller the cache.
The performance of cache memory is frequently measured in terms of its hit ratio. When the processor refers to memory and finds the data in its cache, it is said to produce a hit. If the data is not found in cache, then it is in main memory and is counted as a miss. If a miss occurs, then an allocation is made at the entry indexed by the address of the access. The access can be for loading data to the processor or storing data from the processor to memory. The cached information is retained by the cache memory until it is no longer needed, made invalid or replaced by other data, in which instances the cache entry is de-allocated.
A computer system may utilize one or more levels of cache memory. Allocation and de-allocation schemes implemented for the cache for various known computer systems are generally similar in practice. General practice has been to allocate an entry in the cache for all accesses required by the processor. Accordingly, system architectures specify re-use of accessed data without notion of relevant cache hierarchy level. That is, all accesses are allocated in cache. A disadvantage of this approach is that in certain instances, certain data is referenced once and not reused in the immediate future. It is not desirable for such data, typically termed as non-temporal data, to overwrite data that is used frequently (i.e., temporal data) such as application-cached code and data, when cache memory is full.
BRIEF SUMMARY OF THE INVENTION
A computer system and method for providing cache memory management is disclosed. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
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Chennupaty Srinivas
Huff Thomas
Pentkovski Vladimir
Thakkar Shreekant S.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Hiep T.
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