Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-04-28
2008-10-14
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S136000, C711S145000
Reexamination Certificate
active
07437513
ABSTRACT:
An improvement in performance and a reduction of power consumption in a cache memory can both be effectively realized by increasing or decreasing the number of operated ways in accordance with access patterns. A hit determination unit determines the hit way when a cache access hit occurs. A way number increase/decrease determination unit manages, for each of the ways that are in operation, the order from the way for which the time of use is most recent to the way for which the time of use is oldest. The way number increase/decrease determination unit then finds the rank of the hit ways that have been obtained in the hit determination unit and counts the number of hits for each rank in the order. The way number increase/decrease determination unit further determines increase or decrease of the number of operated ways based on the access pattern that is indicated by the relation of the number of hits to each rank in the order. A way number control unit then selects operation or halt of operation for each way in accordance with the determination to increase or decrease the number of operated ways.
REFERENCES:
patent: 5761715 (1998-06-01), Takahashi
patent: 5918245 (1999-06-01), Yung
patent: 6138209 (2000-10-01), Krolak et al.
patent: 6681297 (2004-01-01), Chauvel et al.
patent: 7127560 (2006-10-01), Cohen et al.
patent: 2003/0084247 (2003-05-01), Song et al.
patent: 1-290051 (1989-11-01), None
patent: H05-020193 (1993-01-01), None
patent: 2554449 (1996-08-01), None
patent: H08-241208 (1996-09-01), None
patent: 9-50401 (1997-02-01), None
patent: H09-050401 (1997-02-01), None
patent: 2000-020396 (2000-01-01), None
patent: 2000-298618 (2000-10-01), None
patent: 2002-049529 (2002-02-01), None
patent: 2002-182980 (2002-06-01), None
patent: 2002-236616 (2002-08-01), None
patent: 2003-131945 (2003-05-01), None
Scheme for Producing Miss-Rate as a Function of Cache Size by Means of Traces Produced by Observing Misses From a Cache of Fixed Size, IBM Technical Disclosure Bulletin, IBM Corp., vol. 33, No. 11, pp. 36-39, Apr. 1, 1991.
Kobayashi Hiroaki
Saida Yasumasa
Bataille Pierre-Michel
Kobayashi Hiroaki
NEC Corporation
Sughrue & Mion, PLLC
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