Cache memory with reduced access time

Details Cache memory with reduced access time Cache memory with reduced access time

1997-10-22

2000-01-11

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711118, G06F 1210

Patent

active

060147326

ABSTRACT:
A cache with a translation lookaside buffer (TLB) that eliminates the need for retrieval of a physical address tag from the TLB when accessing the cache. The TLB includes two content addressable memories (CAM's). For each new cache line, in the tag portion of the cache, instead of storing physical tags, the cache stores vectors called physical hit vectors. Physical hit vectors are generated by a first TLB CAM. Each physical hit vector indicates all locations in the first TLB CAM containing the physical tag of the cache line. For a cache access, a second TLB CAM receives a virtual tag and generates a vector called a virtual hit vector. The virtual hit vector indicates the location in the second TLB CAM of the corresponding virtual tag. Then, instead of retrieving and comparing physical tags, the cache compares a virtual hit vector to a set of physical hit vectors without having to retrieve a physical tag. As a result, one operation is eliminated from a time critical path, reducing the access time. For caches having variable page sizes, an additional CAM structure stores page offset bits and corresponding bit masks from the operating system. Page offset bits are then used to further qualify comparison of virtual hit vectors and physical hit vectors.

REFERENCES:
patent: 4969122 (1990-11-01), Jensen
patent: 5133058 (1992-07-01), Jensen
Lee et al., "Shared Tag for MMU and Cache Memory", IEEE, pp. 77-80, Oct. 11, 1997.

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