Cache memory with a parity write control circuit

Details Cache memory with a parity write control circuit Cache memory with a parity write control circuit

1990-06-18

1991-08-27

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

365200, 365 49, 371 511, G11C 700, G11C 800, G11C 11407

Patent

active

050439430

ABSTRACT:
A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE.sub.x) signals to enable a write amplifier to individually write a single parity bit to a selected memory location. The SRAM is designed to function in either a parity or a non-parity mode. A bonding option pad is connected to parity control logic circuitry, and determines whether the SRAM will function in the parity mode or the non-parity mode. The parity control logic circuitry generates a parity signal, based on the electrical connection of the option pad. Thus, when the option pad is connected to ground, the parity option is selected, whereas, when the option pad is connected to a positive power supply, then non-parity functionality is selected. When parity functionality is selected, the the SRAM will allow the four (4) independent BWE.sub.x signals to individually enable the write amplifier. When non-parity functionality is selected, a single control signal will enable the write amplifier, and the SRAM functions as a standard memory device.

REFERENCES:
patent: 4740971 (1988-04-01), Tam et al.
patent: 4831625 (1989-05-01), Chiu et al.
patent: 4860262 (1989-08-01), Chiu
patent: 4862418 (1989-08-01), Cuppens et al.
patent: 4884270 (1989-11-01), Chiu et al.
patent: 4912630 (1990-03-01), Cochcroft, Jr.

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