Cache memory usable as scratch pad storage

Details Cache memory usable as scratch pad storage Cache memory usable as scratch pad storage

2007-08-21

2007-08-21

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S154000, C711S170000

Reexamination Certificate

active

11188668

ABSTRACT:
A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.

REFERENCES:
patent: 5276835 (1994-01-01), Mohan et al.
patent: 5537574 (1996-07-01), Elko et al.
patent: 5983313 (1999-11-01), Heisler et al.
patent: 6510493 (2003-01-01), Liu et al.
patent: 6574708 (2003-06-01), Hayter et al.

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