Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-12-20
2005-12-20
Batalille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S113000
Reexamination Certificate
active
06978355
ABSTRACT:
Performing a cache only data transfer across a bus connecting a storage apparatus with a host concurrent with a period of bus availability while being incident within a time period for executing a connect host data transfer command. The time period for executing the connect host data transfer command is determined by a combination of a seek latency portion of the connect host data transfer command execution in combination with a rotation latency portion of the connect host data transfer command execution offset by a data transfer latency between the storage apparatus and the host in combination with an overhead time, wherein the overhead time is determined by a time for determining the time period for executing the connect host data transfer command in conjunction with a time for stopping an operation of the storage apparatus and transitioning to a new operation of the storage apparatus.
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Coker Kenny T.
Mowery Philip T.
Batalille Pierre-Michel
Fellers , Snider, et al.
Seagate Technology LLC
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