Cache memory to processor bus interface and method thereof

Details Cache memory to processor bus interface and method thereof Cache memory to processor bus interface and method thereof

1995-03-28

1998-04-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711137, 395872, G06F 1314

Patent

active

057375500

ABSTRACT:
A bus interface unit of a processor system provides an efficient interface between a cache memory, optimized to receive a particular number of bytes per request, and an external bus optimized to provide a different number of bytes per bus transaction. In one embodiment a cache memory requests a memory block of 16-bytes, and in response the bus interface unit executes a bus transaction to instead retrieve 32 bytes from an external memory source. The requested 16 bytes are provided to the cache memory, and the remaining 16 bytes are buffered, along with the starting address of the buffered bytes, by the bus interface unit. A subsequent request from the cache memory for a memory block matching the buffered bytes is handled directly by the bus interface unit, without initiating any external bus transaction. The cache memory need not be aware that the external bus transfers 32 bytes per transaction, rather than the requested 16 bytes. Since the bus interface unit uses physical addresses, the details of cache organization actually used and of any paging schemes are irrelevant. Moreover, little overhead is required and no tight communication with the processor is necessary.

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