Cache memory system with simultaneous access of cache and main m

Details Cache memory system with simultaneous access of cache and main m Cache memory system with simultaneous access of cache and main m

1997-05-02

1998-09-22

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, G06F 1200

Patent

active

058130306

ABSTRACT:
A processing system includes a cache memory system which receives an address and a memory request from a processor. Simultaneously, information is accessed responsive to the address from a main memory and from a cache memory. During access of the information from the main memory and cache memory, it is determined whether the desired information is stored in the cache memory. If so, the information is output from the cache memory; if not, the information is output from the main memory.

REFERENCES:
patent: 3848234 (1974-11-01), MacDonald
patent: 3896419 (1975-07-01), Lange et al.
patent: 4439829 (1984-03-01), Tsiang
patent: 4504902 (1985-03-01), Gallaher et al.
patent: 4567578 (1986-01-01), Cohen et al.
patent: 4586133 (1986-04-01), Steckler
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 4847758 (1989-07-01), Olson et al.
patent: 4858111 (1989-08-01), Steps
patent: 4933835 (1990-06-01), Sachs et al.
patent: 5047920 (1991-09-01), Funabashi
patent: 5097409 (1992-03-01), Schwartz et al.
patent: 5155833 (1992-10-01), Cullison et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5247648 (1993-09-01), Watkins et al.
patent: 5249282 (1993-09-01), Segers
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5285323 (1994-02-01), Hetherington et al.
patent: 5333296 (1994-07-01), Bouchard et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5530833 (1996-06-01), Iyengar et al.
Technical Paper entitled "Processor Performance Enhancement Using a Memory CacheScheme", IBM Technical Disclosure Bulletin, vol. 32, No. 6A, Nov. 1989, pp. 373-379.
Technical Paper entitled "Processor Performance Enhancement Using a Memory CacheScheme", IBM Technical Disclosure Bulletin, vol. 32, No. 6A, Nov. 1989, pp. 373-379.
Chapter entitled "Cache Memory Design", Cypress Semiconductor, pp. 11-31.

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