Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent
1996-03-20
1998-12-01
Swann, Tod R.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
364DIG1, 3642434, 365227, 36518907, 36523003, 39575003, 39575005, 711118, 711136, 711160, G06F 1200, G06F 132
Patent
active
058453091
ABSTRACT:
A cache memory system has an address register for storing a tag address and an index address of data to be accessed, a plurality of data memories for storing data corresponding to said index address, a plurality of tag memories corresponding to said data memories for storing tag addresses relating to said data stored in said data memories, and tag comparators corresponding to said tag memories for comparing a tag address stored in said tag memories with the tag address stored in the address register and for determining whether a cache hit has occurred or a cache miss has occurred. A reference frequency information register stores information indicating a tag memory which has resulted in a cache hit. An access control circuit selects one of the tag memories and one of the comparators corresponding to the selected tag memory based on the information from the reference frequency information register. Only the selected tag memory and the selected tag comparator are operated in order to control a comparison operation of tag addresses and to reduce power consumption.
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Kawasumi Atsushi
Shirotori Tsukasa
Kabushiki Kaisha Toshiba
Swann Tod R.
Thai Tuan V.
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