Cache memory system with dual cache tag memories

Details Cache memory system with dual cache tag memories Cache memory system with dual cache tag memories

1999-12-09

2002-06-25

Bragdon, Reginald G. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000

Reexamination Certificate

active

06412044

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a cache memory system of a computer, and more particularly, to a cache memory system with dual cache tag memories.
2. Description of the Prior Art
Please refer to FIG.
1
.
FIG. 1
is a functional block diagram of a prior art cache memory system
12
of a computer
10
. The computer
10
comprises a processor
14
, a first address bus
16
electrically connected between the processor
14
and the main memory
18
for transmitting a data address
22
which can access one storage cell
20
in the main memory
18
, a first data bus
24
electrically connected between the processor
14
and the main memory
18
for transmitting data, a second address bus
28
electrically connected between the processor
14
and the cache data memory
26
for transmitting the data address
22
, and a second data bus
30
electrically connected between the processor
14
and the cache data memory
26
for transmitting data. The data address
22
contained in the first and second address buses
16
,
28
comprises a low-order portion defined as a cache line address and a high-order portion defined as a block address.
The cache memory system
12
comprises a cache data memory
26
, a cache tag memory
34
, and a cache controller
36
for controlling operations of the cache memory system
12
. The cache data memory
26
is electrically connected between the second address bus
28
and the second data bus
30
, and has a plurality of cache lines
32
for storing data from the main memory
18
. Data stored in each cache line
32
of the cache data memory
26
is accessible by the processor
14
using the cache line address contained in the second address bus
28
.
The cache tag memory
34
is electrically connected to the second address bus
28
and has a plurality of tag cells
38
. Each tag cell
38
of the cache tag memory
34
is correspondent with one cache line
32
of the cache data memory
26
for storing a block address of data stored in the corresponding cache line
32
of the cache data memory
26
.
When accessing the cache memory system
12
, the processor
14
will transmit a data address
22
of data in the main memory
18
to the cache memory system
12
through the second address bus
28
, the cache controller
36
will compare a block address of the data address
22
with a block address
39
stored in a corresponding tag cell
38
. If the block address of the data address
22
and the block address
39
stored in the tag cell
38
have a cache hit, the cache controller
36
will write the data transmitted from the processor
14
through the second data bus
30
into a cache line
32
of the cache data memory
26
corresponding to the cache line address of the data address
22
, or retrieve data stored in the cache line
32
to the processor
14
through the second data bus
30
. If the block address of the data address
22
has a cache miss with the block address
39
stored in the tag cell
38
, the cache controller
36
will initiate a swap procedure to replace the data stored in the cache line
32
of the cache data memory
26
corresponding to the cache line address of the data address
22
with the data stored in a storage cell
20
of the main memory
18
pointed by the data address
22
, and replace the block address
39
stored in the tag cell
38
with the block address of the data address
22
.
Whenever the block address of the data address
22
and the block address
39
stored in the tag cell
38
have a cache miss, the cache controller
36
will swap the data stored in the cache line
32
of the cache data memory
26
, and swap the block address
39
stored in the corresponding tag cell
38
of the cache tag memory
34
. If the processor
14
is to access rarely used data, the cache controller
36
will still initiate the swap procedure, resulting in a high penalty and a low hit rate.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a cache memory system of a computer to solve the above mentioned problem.
Briefly, in a preferred embodiment, the present invention provides a cache memory system of a computer which comprises a processor, an address bus electrically connected to the processor for transmitting a data address which can access one storage cell in the main memory, and a data bus electrically connected to the processor for transmitting data, the data address contained in the address bus comprising a low-order portion defined as a cache line address and a high-order portion defined as a block address, the cache memory system comprising:
a cache data memory, electrically connected between the address bus and the data bus, having a plurality of cache lines for storing data from the main memory, data stored in each cache line of the cache data memory being accessible by the processor using the cache line address contained in the address bus;
a first cache tag memory, electrically connected to the address bus, having a plurality of tag cells, each tag cell of the first cache tag memory being correspondent with one cache line of the cache data memory for storing a block address of data stored in the corresponding cache line of the cache data memory;
a second cache tag memory, electrically connected to the address bus, having a plurality of tag cells, each tag cell of the second cache tag memory being correspondent with one cache line of the cache data memory for storing a block address of the cache line of the cache data memory currently transmitted from the address bus; and
a cache controller for controlling operations of the cache memory system;
wherein when accessing the cache memory system, the processor will transmit a data address of data in the main memory to the cache memory system through the address bus, a first block address stored in a tag cell of the first cache tag memory and a second block address stored in a tag cell of the second cache tag memory corresponding to a cache line address of the data address will be transmitted to the cache controller, and the cache controller will compare a block address of the data address with the first and second block addresses, if the block address of the data address and the first block address have a cache hit, the cache controller will write the data transmitted from the processor through the data bus into a cache line of the cache data memory corresponding to the cache line address of the data address, or retrieve data stored in the cache line to the processor through the data bus, if the block address of the data address has a cache miss with the first block address but has a cache hit with the second block address, the cache controller will initiate a swap procedure to replace the data stored in the cache line of the cache data memory corresponding to the cache line address of the data address with the data stored in a storage cell of the main memory pointed by the data address, if the block address of the data address has cache misses with both the first and second block addresses, the cache controller will control the processor to store the data into the main memory or retrieve the data from the main memory directly, but will not initiate the swap procedure to replace the data stored in the cache data memory, and the cache controller will store the block address of the data address into the tag cell of the second cache tag memory corresponding to the cache line address of the data address.
It is an advantage of the present invention that the cache memory system comprises dual cache tag memories. The data stored in the cache line of the cache data memory corresponding to the cache line address of the data address will be replaced with the data stored in the storage cell of the main memory pointed by the data address only if the processor accesses the data stored in the corresponding storage cell twice consecutively, reducing penalty and increasing hit rate.
These and other objects and the advantages of the present invention will no doubt become obvious to those of ordinary skill in the

Affiliated with

Also associated with

Rating

Cache memory system with dual cache tag memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cache memory system with dual cache tag memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory system with dual cache tag memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2944799