Cache memory system including a partially hashed index

Electrical computers and digital processing systems: memory – Address formation – Hashing

Reexamination Certificate

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Details

C711S118000, C711S122000, C711S127000, C711S206000, C711S217000, C711S220000

Reexamination Certificate

active

07606994

ABSTRACT:
In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the address for accessing a particular entry within the cache memory. More particularly, the cache controller may generate the index value by performing a hash function on a first portion of the address such as an address tag, and combining a result of the hash function with a second portion of the address such as an index, for example.

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Mazen Kharbutli, Keith Irwin, Yan Solihin and Jaejin Lee,Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses, 10th International Symposium on High Performance Computer Architecture (HPCA '04), Feb. 2004, hpca, p. 288.

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