Cache memory system having high and low speed and power consumpt

Details Cache memory system having high and low speed and power consumpt Cache memory system having high and low speed and power consumpt

1997-02-12

1999-07-06

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39575004, 39575006, 395556, G06F 1300, G06F 132

Patent

active

059208880

ABSTRACT:
A cache memory automatically sets a low-, semi-, or high-speed mode operation according to a result of comparison between a half-period of a reference clock signal and a pulse width of a reference pulse signal provided by a reference pulse signal generator. Namely, a start signal generator generates a start signal used to access data memories, according to the frequency of the reference clock signal and a difference between the reference clock and pulse signals. According to the start signal and information indicating a hit tag memory, the cache memory dynamically switches the modes from one to another, without external instructions to the cache memory. In one embodiment, the cache memory is an n-way set associative cache memory having a plurality of data memories, and an enable signal is supplied only to a data memory associated with the hit tag memory when receiving hit information before a low speed mode start signal, or to all of the data memories when receiving the hit information after the high-speed mode start signal.

REFERENCES:
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5682515 (1997-10-01), Lau et al.
patent: 5715426 (1998-02-01), Takahashi et al.
patent: 5717892 (1998-02-01), Oldfield
patent: 5752045 (1998-05-01), Chen
patent: 5761715 (1998-06-01), Takahashi
patent: 5778428 (1998-07-01), Batson et al.

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