Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1993-11-23
2001-01-30
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000
Reexamination Certificate
active
06182194
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a cache memory and more particularly to a cache memory which makes a computer system quicker by reducing cache misses.
2. Description of the Related Art
Many conventional cache memories are expensive and have hence been used in only a limited part of the computer system. But as advances have been made in process technology, application of more inexpensive memories has been on the increase recently. Meanwhile the quicker the CPU, the higher the price which had to be paid for cache mistakes; consequently using cache memories would be a key to the performance of computer systems.
The conventional technology for minimizing cache mistakes and making purge and load of data quicker is exemplified by the following prior art:
Japanese Patent Laid-Open Publication No. SHO 60-79446 discloses a concept of putting a task identifier with data to be accessed in the cache memory only when a logical address to be accessed and the task identifier coincide with each other. Japanese Patent Laid-Open Publication No. SHO 62-145341 discloses a concept of dividing the cache memory into a shared space area and a multi-space area so that purge of these divided areas can be respectively controlled. According to these prior concepts, overhead accompanying replacing of cache data is minimized in an effort to make purge and load of data quicker and more effective.
Japanese Patent Laid-Open Publication No. HEI 4-18649 discloses a concept of maintaining data of the designated cache memory area in a simple cache memory for a disc equipment having no LRU algorithm, improving the rate of processing write/read commands.
Under the foregoing circumstances, in order to realize a quick computer system, it should minimize cache mistakes or should effectively use CPU latency for the cache memory.
SUMMARY OF THE INVENTION
With the foregoing problems in mind, it is an object of this invention to provide a cache memory which minimizes cache mistakes to make a computer system quicker.
In order to accomplish the above object, according to a first aspect of the invention, there is provided a cache memory, which is adapted to be situated adjacent to a CPU, for storing part main memory data to make the CPU quicker, the cache memory comprising: one or more memory areas in which different main memory data is to be stored; and a register, situated between a cache internal address data bus and the respective memory areas, for storing access information of the data in the respective memory areas, whereby access is made to selected data only.
According to a second aspect of the invention, there is provided a cache memory, which is adapted to be situated adjacent to a CPU, for storing part of main memory data to make the CPU quicker, the cache memory comprising: one or more first memory areas in which different main memory data is stored; a register situated between a cache internal address data bus and the respective first memory areas for storing access information of the data on the respective first memory areas; and a second memory area which is connected to the cache internal address data bus and in which data shared among tasks running in the system, whereby access is made to selected data only.
According to a third aspect of the invention, there is provided a cache memory, which is adapted to be situated adjacent to a CPU, for storing part of data in a main memory to make the CPU quicker, the cache memory comprising: a register which is situated on a cache internal address data bus and in which address areas inhibiting any ejection of the data in the cache memory are stored; and a memory area in which the data in the main memory and a flag showing any inhibited ejection of the data, whereby an address area in the main memory is designated to inhibit any ejection of data.
With the first arrangement, in switching the context, if a task to be dispatched is recognized as existing in any of the memory areas by referring to a task identifier, the memory area in which the task is stored will be selected. If a task to be dispatched does not exist in any memory area, the task will be loaded in the memory area selected from the replaceable memory areas by referring to a replaceable flag. If the replaceable flag is set to be not replaceable, the data in the memory area will not be replaced.
With the second arrangement, since the second memory area in which data such as shared data, unlikely to be purged or likely to remain permanently, is connected to the cache internal address data bus independently of the first memory area in which user data is stored, it is possible to make the computer system quicker.
Thus since the data in the memory area is replaced by referring to access information, it is possible to minimize cache mistakes.
With the third arrangement, since a value indicating inhibited ejection of data may be set with the flag corresponding to the data stored in the memory area, then it is possible to inhibit ejection of data. If there is an ejection inhibit area, the start and end addresses of such a range is stored in the register. If there is no ejection inhibit area, an initial value which indicates no inhibit area has been specified is set in the register. Since a high-frequency-access program such as a system program is set to ejection inhibit so as to be permanent, it is possible to minimize cache mistakes.
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“Cache Subsystem,” Intel 80386 Hardware Reference Manual, Intel. Co., pp. 7-6 to 7-8, 1986.
Hennessey et al., “Computer Architecture,” Morgan Kaufmann Publishers, 1990, pp. 408-409.
Sakakura Takashi
Uemura Jose
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Hiep T.
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