Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-07-02
2009-06-02
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S173000
Reexamination Certificate
active
07543113
ABSTRACT:
A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.
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Brummel Karl
Soltis, Jr. Donald C.
Walker Shawn
Ellis Kevin L
Hewlett--Packard Development Company, L.P.
Thammavong Prasith
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