Cache memory system, and control method therefor

Details Cache memory system, and control method therefor Cache memory system, and control method therefor

2011-05-31

2011-05-31

Choe, Yong (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S123000

Reexamination Certificate

active

07953935

ABSTRACT:
A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

REFERENCES:
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5524225 (1996-06-01), Kranich
patent: 5860110 (1999-01-01), Fukui et al.
patent: 6173392 (2001-01-01), Shinozaki
patent: 7246204 (2007-07-01), Shirahige et al.
patent: 2002/0069331 (2002-06-01), Chauvel et al.
patent: 2004/0003179 (2004-01-01), Shirahige et al.
patent: 2004/0215896 (2004-10-01), McCalpin et al.
patent: 2005/0193058 (2005-09-01), Yasuda et al.
patent: 2007/0028055 (2007-02-01), Tanaka et al.
patent: 2007/0083718 (2007-04-01), Okabayashi
patent: 2007/0136530 (2007-06-01), Tanaka
patent: 2007/0143548 (2007-06-01), Nakanishi et al.
patent: 2007/0186048 (2007-08-01), Nakanishi et al.
patent: 0557884 (1993-09-01), None
patent: 0602808 (1994-06-01), None
patent: 1182566 (2002-02-01), None
patent: 5119453 (1976-02-01), None
patent: 60-45855 (1985-03-01), None
patent: 6-12327 (1994-01-01), None
patent: 2004-118305 (1994-04-01), None
patent: 7-84879 (1995-03-01), None
patent: 7-295882 (1995-11-01), None
patent: 11-167520 (1999-06-01), None
patent: 11-272551 (1999-10-01), None
patent: 2003223360 (2003-08-01), None
patent: 2004-38345 (2004-02-01), None
patent: 2004-326758 (2004-11-01), None
patent: 4008946 (2007-09-01), None
patent: 4008947 (2007-09-01), None
patent: 4009306 (2007-09-01), None
patent: 2005050454 (2005-06-01), None
patent: 2005050455 (2005-06-01), None
patent: 2005066796 (2005-07-01), None
patent: 2005091146 (2005-09-01), None
English language Abstract of JP 6-12327.
English language Abstract of JP 2003-223360.
English language Abstract of JP 2004-326758.
English language Abstract of JP 11-272551.
English language Abstract of JP 11-167520.
English language Abstract of JP 7-295882.
U.S. Appl. No. 11/910,831 to Yamamoto et al., filed Oct. 5, 2007.
English Language Abstract of JP 2004-118305.
English Language Abstract of JP 2004-38345.
English Language Abstract of JP 7-84879.
English Language Abstract of JP 60-45855.
U.S. Appl. No. 10/577,133.
English Language Abstract of WO 2005/091146.
English language translation of Japanese Office action dated Nov. 13, 2007.

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