Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-09-13
2009-02-17
Sough, Hyung S (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S141000
Reexamination Certificate
active
07493445
ABSTRACT:
To improve the efficiency of access to a system memory associated with changes (writes) to cache data, a cache line having the same memory size as write data is selected and the write data is written into the selected cache line, thereby reducing the number of accesses to the system memory to cache data from the system memory associated with partial replacement of cache lines. Further, valid data at an address contiguous with the address of the write data is combined with the write data, and written into a cache line having the same size as the combined data, thereby reducing the number of accesses to the system memory to flush data from the cache associated with writes to the cache.
REFERENCES:
patent: 4315312 (1982-02-01), Schmidt
patent: 5588129 (1996-12-01), Ballard
patent: 5802572 (1998-09-01), Patel et al.
patent: 2002251322 (2006-09-01), None
Chery Mardochee
International Business Machines - Corporation
LeStrange Michael
Sough Hyung S
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