Cache memory system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S128000

Reexamination Certificate

active

06950902

ABSTRACT:
A cache memory system having a small-capacity and high-speed access cache memory provided between a processor and a main memory, including a software cache controller for performing software control for controlling data transfer to the cache memory in accordance with a preliminarily programmed software and a hardware cache controller for performing hardware control for controlling data transfer to the cache memory by using a predetermined hardware such that the processor causes the software cache controller to perform the software control but causes the hardware cache controller to perform the hardware control when it becomes impossible to perform the software control.

REFERENCES:
patent: 6131145 (2000-10-01), Matsubara et al.
Jim Handy, The Cache Memory Book, 1998, Academic Press Inc., 2nd ed., pp 51-54.
Takashi Fujiwara et al, A Custom Processor for the Multiprocessor System ASCA, 1998, IASTED 16thInternational Conference on Applied Informatics, pp 258-261.
Jim Handy, The Cache Memory Book, 1998, Academic Press Inc., 2nded., pp 44-47, 204.
Erik G. Hallnor et al, A Fully Associative Software-Managed Cache Design, 2000, ACM Press, pp 107-116.
Sakamoto, Katsuto., et al. “Software Controlled Cache for Multi-grain Parallel Processing.” The Institute of Electronics, Information and Communications Engineers, Technical Report of IEICE, ICD98-26, CPSY98-11-26, Apr. 4, 24, 1998, pp. 117-124.
Iwai, K., et al. “ ASCA: A multiprocessor architecture Intitiated by a compiler.” Joint Symposium on Parallel Processing 2000, JSPP2000, May 12, 2000, pp. 3-10.
Nakamura, Hiroshi., et al. “SCIMA: A New Architecture for High Performance Computing.” Proceedings of Information Processing Society of Japan; Transactions on High Performance Computing Systems. Aug. 15, 2000, vol. 41. No.: SIG5(HPS1) pp. 15-27.
“Reducing Memory Penalty by a Programmable Prefetch Engine for On-Chip Caches” Tien-Fu ChenMicroprocessors and MicrosystemsV.21 No. 2 (Oct. 1, 1997) pp. 121-130.
“SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing” Masaki Kondo et al., International Conference on Computer Design in Austin, TX (Sep. 17-20, 2000) pp. 105-111.
“SCIMA: A Novel Processor Architecture for High Performance Computing” Masaki Kondo High Performance Computing in the Asia-Pacific Region http://ieeexplore.ieee.org/ie15/6804/18265/00846477.pdf (May 14-17, 2000) pp. 355-360.

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