Cache memory self test

Details Cache memory self test Cache memory self test

2005-11-15

2005-11-15

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000, C714S734000, C711S144000

Reexamination Certificate

active

06966017

ABSTRACT:
The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

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