Cache memory reset responsive to change in main memory

Details Cache memory reset responsive to change in main memory Cache memory reset responsive to change in main memory

1987-08-05

1989-08-22

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Erase

371 49, 36518901, G11C 700

Patent

active

048602620

ABSTRACT:
A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are set to the same level and a parity bit is set to a value corresponding to parity in the multi-bit word. The circuit includes a parity generator which receives a multi-bit input data word and generates at least one parity bit therefrom. During a normal write operation, the multi-bit input data word and the parity bit are written into the digital memory at the selected address. During a word reset signal, output from the parity generator and the multi-bit input data word are blocked from entry into the memory.

REFERENCES:
patent: 4099069 (1978-07-01), Cricchi et al.
patent: 4155070 (1979-05-01), Munter

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