Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2005-01-19
2010-08-24
Chaudry, M. Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S764000
Reexamination Certificate
active
07783939
ABSTRACT:
A cache memory built in a processor comprising a plurality of independent memory blocks, pass/fail information memory unit memorizing a presence/absence of a failure occurring in each of the memory blocks, and a screening control function substituting a sound memory block for a failed memory block based on a memory content in the pass/fail information memory unit.
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Sakurai Hitoshi
Tonosaki Mie
Chaudry M. Mujtaba K
Fujitsu Limited
Fujitsu Patent Center
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