Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-02-10
2008-07-22
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S121000, C711S119000, C711S124000
Reexamination Certificate
active
07404046
ABSTRACT:
A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.
REFERENCES:
patent: 6418514 (2002-07-01), Arimilli et al.
Goodman Benjiman L.
Guthrie Guy L.
Starke William J.
Williams Derek E.
Dillon & Yudell LLP
Gerhardt Diana R.
Peikari B. James
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