Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-10-25
2005-10-25
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000, C711S134000, C711S144000, C711S145000
Reexamination Certificate
active
06959363
ABSTRACT:
A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.
REFERENCES:
patent: 5499355 (1996-03-01), Krishnamohan et al.
patent: 5600817 (1997-02-01), Macon, Jr. et al.
patent: 5649144 (1997-07-01), Gostin et al.
patent: 6134643 (2000-10-01), Kedem et al.
patent: 6138213 (2000-10-01), McMinn
patent: 6292871 (2001-09-01), Fuente
patent: 6523093 (2003-02-01), Bogin et al.
patent: 2002/0087802 (2002-07-01), Al-Dajani et al.
patent: 2003/0033488 (2003-02-01), Gruner et al.
patent: 2004/0049640 (2004-03-01), So et al.
Hedinger Peter
Southwell Trefor
de Guzman Dennis M.
Jorgenson Lisa K.
Peugh Brian R.
Seed IP Law Group PLLC
STMicroelectronics Limited
LandOfFree
Cache memory operation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache memory operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache memory operation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3439330