Cache memory management

Details Cache memory management Cache memory management

2006-05-16

2006-05-16

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C711S141000, C711S003000

Reexamination Certificate

active

07047364

ABSTRACT:
Management of accessing data in a main memory and a cache memory includes, for each unit of data transferred from a first processor to a second processor, filling a cache set of the cache memory with data associated with addresses in the main memory that correspond to the cache set after the first processor writes a unit of data to addresses that correspond to the cache set. For each unit of data transferred from the second processor to the first processor, filling the cache set with data associated with addresses in the main memory that correspond to the cache set before the first processor reads a unit of data written by the second processor to addresses that correspond to the cache set. The data used to fill the cache set are associated with addresses that are different from the addresses associated with the unit of data.

REFERENCES:
patent: 5796996 (1998-08-01), Temma et al.
patent: 6003116 (1999-12-01), Morita et al.
patent: 6397305 (2002-05-01), Knight et al.
patent: 2002/0038408 (2002-03-01), Metayer et al.
patent: 2003/0140199 (2003-07-01), Kunkel et al.

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