Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-04-12
1998-06-09
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711 3, 711136, 711145, 711160, G06F 1200
Patent
active
057651906
ABSTRACT:
A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15) If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
REFERENCES:
patent: 5058003 (1991-10-01), White
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5131083 (1992-07-01), Crawford et al.
patent: 5133058 (1992-07-01), Jensen
patent: 5233702 (1993-08-01), Emma et al.
patent: 5235688 (1993-08-01), Taniguchi et al.
patent: 5249282 (1993-09-01), Seger
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5355467 (1994-10-01), MacWilliam et al.
patent: 5367660 (1994-11-01), Gat et al.
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5410669 (1995-04-01), Biggs et al.
patent: 5526510 (1996-06-01), Akkary et al.
patent: 5551001 (1996-08-01), Cohen et al.
Bibikar Vasudev J.
Circello Joseph C.
Tirumala Anup S.
Motorola Inc.
Swann Tod R.
Thai Tuan V.
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