Cache memory having pipeline structure and method for...

Details Cache memory having pipeline structure and method for... Cache memory having pipeline structure and method for...

2007-10-24

2010-11-16

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07836253

ABSTRACT:
A cache memory arranged between a processor and a low-speed memory and performing a pipeline processing of a memory access made by the processor. In a first stage, the cache memory reads out a tag address from a tag memory. In a second stage, the cache memory performs a hit decision by a hit decision unit. When the hit decision result is a miss hit, the cache memory performs an update control of the tag memory and a behavior control of a bypass circuit for supplying a data held in a latch circuit to the hit decision unit by bypassing the tag memory in a third stage. The latch circuit is configured to hold a tag address included in a input address supplied from the processor.

REFERENCES:
patent: 2004/0024967 (2004-02-01), Zhang
patent: 1 361 518 (2003-11-01), None
patent: 10-063575 (1998-03-01), None

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